Fabrication method of semiconductor integrated circuit device

ABSTRACT

On the occasion of the aligning process to transfer a predetermined pattern to a semiconductor wafer by irradiating a photoresist on the semiconductor wafer with an aligning laser beam of the modified lighting via a photomask MK, the photomask MK allocating, to provide periodicity, the main apertures to transfer the predetermined pattern as the apertures formed by removing a part of the half-tone film on the mask substrate and the auxiliary apertures not resolved on the semiconductor wafer as the apertures formed by removing a part of the half-tone film is used to improve the resolution of the pattern.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for fabricating asemiconductor integrated circuit device (hereinafter called asemiconductor IC device) and particularly to the technique that can beeffectively adapted to photolithography (hereinafter, simply referred toas lithography) to transfer a predetermined pattern to a semiconductorwafer (hereinafter, simply referred to as wafer) using a photomask(hereinafter, simply referred to as mask) in the manufacturing processof a semiconductor IC device.

[0002] In the manufacturing of a semiconductor IC device, thelithography technique is used as a method for transferring a finepattern to a wafer. In the lithography technique, a projection aligneris mainly used to form a device pattern by transferring to the wafer thepattern of a mask mounted on the projection aligner.

[0003] This lithography technique is described, for example, in theJapanese Unexamined Patent Publication No. 135402/1999. Namely, thisreference discloses the technique for allocating an auxiliary aperturein such a degree as not resolved in the periphery of a main apertureprovided to form a contact hole of a memory device in the mask and forutilizing a modified lighting or the like for the exposing process.

[0004] However, the inventors of the present invention have found thelithography technique explained above is accompanied with the followingproblems.

[0005] Namely, with improvement in the scale-down, margin for depth offocus decreases and thereby resolution of patterns is lowered. Moreover,when a coarse region wherein patterns are discretely allocated on thesame layer and a fine region wherein patterns are closely allocatedcoexist at the same time, a difference is generated in the pattern sizesof such coarse region and fine region. Moreover, size accuracy ofpatterns existing at the boundary between the coarse region and fineregion is deteriorated.

SUMMARY OF THE INVENTION

[0006] Therefore, an object of the present invention is to provide thetechnique to improve resolution of patterns.

[0007] Moreover, another object of the present invention is to providethe technique to reduce size difference of patterns in the coarse regionand fine region.

[0008] Still another object of the present invention is to provide thetechnique to improve size accuracy of patterns existing at the boundaryof the coarse region and fine region.

[0009] The abovementioned objects and the other objects and novelcharacteristics of the present invention will become more apparent fromthe description of the present specification and the accompanyingdrawings.

[0010] The summary of the representative inventions disclosed in thepresent specification will be briefly explained as follows.

[0011] Namely, the present invention utilizes, on the occasion of thealigning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating the photoresist film on thesemiconductor wafer with an aligning light beam of a modified lightingvia a photomask, the photomask allocating, to provide periodicity, mainapertures to transfer the predetermined pattern that are the aperturesformed by removing a part of a half-tone film on a mask substrate andauxiliary apertures not resolved on a semiconductor wafer that are theapertures formed by removing a part of the half-tone film.

[0012] Moreover, the present invention utilizes a photomask in whichmain apertures to transfer the predetermined pattern that are formed asthe apertures by removing a part of a light shielding film on the masksubstrate and auxiliary apertures not resolved on the semiconductorwafer that are the apertures formed by removing a part of the lightshielding film are allocated to provide periodicity on the occasion ofthe aligning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating the photoresist film on thesemiconductor wafer with the aligning laser beam of the modifiedlighting via the photomask, in view of realizing the proximitycorrection to the predetermined main apertures among the main apertures,predetermined auxiliary apertures among the auxiliary apertures or toboth apertures.

[0013] Moreover, the present invention utilizes, on the occasion ofaligning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating a photoresist film on thesemiconductor wafer with an aligning laser beam of the modified lightingvia the photomask, the photomask thereof allocating, to provideperiodicity, main apertures to transfer the predetermined pattern whichare the apertures formed by removing a part of the light shielding filmon the mask substrate and auxiliary apertures not resolved on thesemiconductor wafer that are the aperture formed by removing a part ofthe light shielding film and also forming the auxiliary apertureallocation region as the region broadened for integer times of the pitchof the predetermined pattern with reference to the main apertures.

[0014] Moreover, the present invention discloses a structure that thecoarse region where the predetermined relatively coarse pattern isallocated and the fine region where the predetermined relatively finepattern is allocated coexist in the same layer in the predeterminedregion of the semiconductor wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a plan view of the essential portion of a semiconductorIC device as an embodiment of the present invention.

[0016]FIG. 2(a) is a plan view of the essential portion of a photomaskused to transfer a pattern of the semiconductor IC device of FIG. 1.

[0017]FIG. 2(b) is a cross-sectional view among the line A1—A1 of FIG.2(a).

[0018]FIG. 3 is a plan view of the essential portion of thesemiconductor IC device as an embodiment of the present invention.

[0019]FIG. 4(a) is a plan view of the essential portion of the photomaskused to transfer a pattern of the semiconductor IC device of FIG. 3.

[0020]FIG. 4(b) is a cross-sectional view along the line A2—A2 of FIG.4(a).

[0021]FIG. 5(a) is a plan view of the essential portion in themanufacturing process of the semiconductor IC device using the photomaskof FIG. 4(a).

[0022]FIG. 5(b) is a cross-sectional view along the line A3—A3 of FIG.5(a).

[0023]FIG. 6(a) is a plan view of the essential portion in themanufacturing process of the semiconductor IC device following thecircuit of FIG. 5(a).

[0024]FIG. 6(b) is a cross-sectional view along the line A3—A3 of FIG.6(a).

[0025]FIG. 7(a) is a plan view of the essential portion in themanufacturing process of the semiconductor IC device following thecircuit of FIG. 6(a).

[0026]FIG. 7(b) is a cross-sectional view along the line A3—A3 of FIG.7(a).

[0027]FIG. 8(a) is a plan view of the essential portion in themanufacturing process of the semiconductor IC device following thecircuit of FIG. 7(a).

[0028]FIG. 8(b) is a cross-sectional view along the line A3—A3 of FIG.8(a).

[0029]FIG. 9(a) is a plan view of the essential portion of the fineregion of the semiconductor IC device including CMIS-logic as anembodiment of the present invention.

[0030]FIG. 9(b) is a cross-sectional view along the line A4—A4 of FIG.9(a).

[0031]FIG. 10(a) is a plan view of the essential portion of a patterntransfer mask of the semiconductor IC device of FIG. 9(a).

[0032]FIG. 10(b) is a cross-sectional view along the line A5—A5 of FIG.10(a).

[0033]FIG. 11 is a plan view of the essential portion of the fine regionof the semiconductor IC device including the DRAM-logic hybrid circuitas an embodiment of the present invention.

[0034]FIG. 12 is a cross-sectional view along the line A6—A6 of FIG. 11.

[0035]FIG. 13 is an explanatory diagram of an example of an aligner usedfor manufacturing of the semiconductor IC device as an embodiment of thepresent invention.

[0036]FIG. 14(a) is a plan view of the 4-aperture lighting as an exampleof the lighting system of the aligner of FIG. 13.

[0037]FIG. 14(b) is a plan view of the ring belt lighting as anotherexample of the lighting system of the aligner of FIG. 13.

[0038]FIG. 15 is a graph indicating dependence on deviation of focalpoint of the hole diameter in the present invention and discussionexample.

[0039]FIG. 16 is a graph indicating dependence on exposure of holepattern diameter in the coarse region in the present invention anddiscussion example.

[0040]FIG. 17 is a plan view of the essential portion of a waferincluding the hole patterns formed using the photomask in the otherembodiment of the present invention.

[0041]FIG. 18(a) is a plan view of the essential portion of an exampleof photomask used to form a hole pattern of FIG. 17.

[0042]FIG. 18(b) is a cross-sectional view along the line A7—A7 of FIG.18(a).

[0043]FIG. 19 is a plan view of the essential portion of the waferincluding the hole patterns formed using the photomask as the otherembodiment of the present invention.

[0044]FIG. 20(a) is a plan view of the essential portion of an exampleof the photomask used to form the hole patterns of FIG. 19.

[0045]FIG. 20(b) is a cross-sectional view along the line A8—A8 of FIG.20(a).

[0046]FIG. 21 is an explanatory diagram for explaining a method ofallocating pattern on the photomask as an embodiment of the presentinvention.

[0047]FIG. 22(a) is a plan view of the essential portion of thephotomask on which a pattern is allocated depending on the allocationmethod of FIG. 21.

[0048]FIG. 22(b) is a cross-sectional view along the line A9—A9 of FIG.22(a).

[0049]FIG. 23 is a plan view of the essential portion of the waferincluding hole patterns formed using the photomask as the otherembodiment of the present invention.

[0050]FIG. 24(a) is a plan view of the essential portion of an exampleof the photomask used to form the hole patterns of FIG. 23.

[0051] FIGS. 24(b) and 24(c) are explanatory diagrams indicatingcorrection for the main aperture 3 when the pattern allocation is fineand coarse.

[0052]FIG. 25 is a plan view of the essential portion of the waferincluding hole patterns formed using the photomask as the otherembodiment of the present invention.

[0053]FIG. 26 is a plan view of the essential portion of an example ofthe photomask used to form the hole patterns of FIG. 25.

[0054]FIG. 27 is a plan view of an example of the lighting system of thealigner used to transfer the hole patterns of FIG. 25.

DETAILED DESCRIPTION OF THE INVENTION

[0055] Prior to detailed explanation of the present invention, theterminology in the present specification will be explained first.

[0056] 1. Mask (optical mask):

[0057] Mask has a pattern to shield the light beam and a pattern tochange the phase of light beam formed on the mask substrate. The maskalso includes a reticle on which a pattern in the size equal to severaltimes the actual size is formed. The terms “on the mask substrate”include the upper surface of mask substrate, internal regionapproximated to the upper surface or the space above the upper surfaceof the mask substrate (allocation on the other substrate approximated tothe upper surface is also included). The first main surface of maskmeans the pattern surface where a pattern for shielding the light beamand a pattern for changing the phase of the light beam are formed andthe second main surface of mask means the surface in the opposite sideof the first main surface. A usual mask (binary mask) means an ordinaryphotomask where a mask pattern is formed on the substrate with a patternto shield the light beam and a pattern to transmit the light beam.

[0058] 2. Main aperture:

[0059] An aperture pattern on the mask or the like corresponding to thepattern of device actually transferred to the wafer.

[0060] 3. Auxiliary aperture:

[0061] In general, aperture pattern on the mask not forming theindependent image corresponding to the aperture pattern when projectedon the wafer.

[0062] 4. Half-tone region, half-tone film:

[0063] Region or film having the low light transmitting coefficient notsensitizing the photoresist film by itself. This region or film can beclassified into the in-phase and inverse-phase (inverted) region orfilm. In general, these region and film have the light transmittingcoefficient of 3% to 15% but it is also possible to obtain the half-toneregion or film having the light transmitting coefficient as high as 20%or more through coexistence of a light shielding region or the like.

[0064] 5. “Light transmitting region”, “light transmitting pattern”,“transparent region”, “transparent film” may be used when such region,pattern, film or condition has the optical characteristic allowing thelight beam of 60% or more among those radiating the region to pass. Ingeneral, those allowing the light beam of 90% or more to pass are used.On the other hand, “light shielding region”, “light shielding pattern”,“light shielding film” or “light shielding” may be used when suchregion, pattern, film or condition has the optical characteristicallowing the light beam of less than 40% among those radiating theregion to pass. In general, those allowing the light beam of less thanseveral percentages to 30% (optical transmitting coefficient is almost0% (typically, 1% or less) ) to pass are used. From the functionalviewpoint, the light transmitting region can be defined as the regionhaving the light transmitting coefficient lower than that of thehalf-tone region.

[0065] 6. Ultraviolet ray:

[0066] In the semiconductor field, the ultraviolet ray means theelectromagnetic ray in the wavelength from 400 nm to 50 nm or less inthe short wavelength. The wavelength region longer than 300 nm is calledthe near ultraviolet ray region, the wavelength region shorter thanabove region is called the far ultraviolet ray region and the wavelengthregion of 200 nm or less is called the outside region of the vacuumultraviolet ray region. As a light source, the i-ray of silver arc lamp(wavelength: 365 nm), KrF excimer laser (wavelength: 248 nm), ArF(wavelength: 193 nm) and F2 (wavelength: 157 nm) excimer laser or thelike may be used.

[0067] 7. Wafer or semiconductor substrate means a silicon singlecrystal substrate (in general, a flat disc type substrate), sapphiresubstrate, glass substrate, other insulation/non-insulation orsemiconductor substrate or the like and the composite substrate of thesesubstrates to be used for manufacturing of semiconductor IC device.Moreover, a semiconductor IC device in the present invention includes,unless otherwise particularly specified clearly, the semiconductor ICdevice fabricated on the other insulated substrate such as glassmaterial like TFT (Thin-Film-Transistor) and STN (Super-Twisted-Nematic)liquid crystal or the like in addition to those fabricated on thesemiconductor or insulated substrate such as silicon wafer or sapphiresubstrate or the like.

[0068] 8. Scanning exposure:

[0069] Exposing (aligning) method to transfer the circuit pattern on thephotomask to the desired area on the semiconductor wafer by relativelyand continuously moving (scanning) the aligning belt like a narrow slitin the orthogonal direction (or may be diagonally) to the longitudinaldirection of the slit for the semiconductor wafer and photomask (orreticle, the photomask in the present invention indicates a wide conceptincluding the reticle).

[0070] 9. Step and scan exposure:

[0071] An aligning method for aligning the entire part of the wafer tobe aligned through combination of the scanning exposure and steppingexposure. This aligning method means the aligning concept lower than thescanning exposure.

[0072] 10. Step and repeat exposure:

[0073] An aligning method for transferring the circuit pattern on themask to the desired area on the wafer by stepping repeatedly the waferto the projected image of the circuit pattern on the mask.

[0074] 11. Ordinary lighting means a non-modified lighting in whichlight intensity distribution is comparatively uniform.

[0075] 12. Modified lighting means the lighting system where the lightintensity at the center is lowered and includes the ultra-highresolution technique based on the inclined lighting, ring-belt lighting,multi-pole lighting such as four-pole lighting and five-pole lighting orthe like and a pupil filter equivalent to such multi-pole lighting.

[0076] 13. Resolution:

[0077] Pattern size can be expressed through standardization with thenumerical aperture NA of projection lens and aligning wavelength λ.Since the resolution R is expressed R=K1·λ/NA, it may be used throughconversion. However, since depth of focus D is expressed asD=K2·λ/(NA)², the depth of focus is different. K1 and K2 are constants.

[0078] 14. Transfer pattern:

[0079] A pattern transferred on the wafer with the mask. In morepractical, the photoresist pattern and the pattern actually formed onthe wafer using the photoresist pattern as the mask.

[0080] 15. The photoresist pattern means a film pattern that has beenobtained by patterning a photosensitive organic film with thelithography method. This pattern includes only a resist film having noaperture for the relevant part.

[0081] 16. Hole pattern:

[0082] Fine pattern of contact hole and through hole or the like havingthe two-dimensional size similar to or smaller than the aligningwavelength on the wafer. In general, this pattern is the square shape,or rectangular shape near the square shape or octagonal shape on themask, but it is often circular shape on the wafer.

[0083] 17. Line pattern:

[0084] Pattern of wirings or the like having the belt type patternextending in the predetermined direction.

[0085] In the description of the preferred embodiments, the presentspecification will be explained through division into a plurality ofsections or embodiments whenever required, but unless otherwiseindicated clearly, these are related with each other and one is in therelationship as the modification example, detail or complementaryexplanation of the others.

[0086] Moreover, when the explanation refers to the number of elements(including number, numerical value, quantity, range or the like), unlessotherwise clearly indicated and restricted to the particular number fromthe viewpoint of the principle, such number is not limited to theparticular number and may be larger or smaller than the particularnumber.

[0087] Moreover, in the following preferred embodiments, the structuralelements (including the element step or the like) is not of courseessential, unless otherwise specified clearly and thought as clearlyessential from the viewpoint of the principle.

[0088] In the same manner, in the following preferred embodiments, whenthe present specification refers to the shape and positionalrelationship of structural elements, such shape and positionalrelationship are substantially similar to or resemble with each other,unless otherwise clearly specified or thought as different from theviewpoint of principle. It can also be adapted to the numerical valueand range.

[0089] In addition, the like elements having the similar functions aredesignated with the like reference numerals and the same explanationwill be never repeated in the present specification.

[0090] Moreover, even in the plan views that schematically illustratethe mask or data in the drawings used to explain the preferredembodiments, the half-tone region (or film) and the desired pattern arehatched to assure easier understanding of the drawings.

[0091] The preferred embodiments of the present invention will beexplained in detail with reference to the accompanying drawings.

[0092] (Embodiment 1)

[0093] In manufacturing of a semiconductor IC device, margin of aligningwill be lowered in some cases due to the scale-down at the time offorming a hole pattern as a result of coexistence of the coarse regionand fine region in the same layer.

[0094] Therefore, in this embodiment, for example, a main aperture fortransfer of hole pattern and an auxiliary aperture not resolved byitself in the periphery of the main aperture are allocated at theintersecting point of the virtual lines which are crossing with eachother on the mask. Moreover, the main aperture and auxiliary apertureare formed by removing a part of the halftone film on the mask. Inaddition, as the lighting for the aligning, the modified lighting havingthe usefulness in the periodic pattern is utilized. Thereby, since depthof focus and aligning allowance can be improved in both coarse regionand fine region, resolution of pattern can be improved. Moreover, use ofa half-tone film reduces variation in size resulting from deviation offocus. In addition, a pattern size difference resulting from coarse orfine pattern condition can also be reduced. Furthermore, in the case ofmask using a light shielding film, the auxiliary aperture of mask issometimes resolved on the wafer for the predetermined exposure, but itis possible that the auxiliary aperture of mask is not resolved to thewafer by utilizing the half-tone film.

[0095]FIG. 1 illustrates an example of the allocation on the plane ofthe hole patterns (hatched portions) H in the fine region on the waferW. The hole patterns H are allocated at the intersecting points of thevirtual lines Xw and Yw. The virtual lines Xw, Yw are crossing inorthogonal with each other. The pitches Dwx, Dwy of the virtual linesXw, Yw are equal and these virtual lines Xw and Yw are allocated in thepitch equal to that of the integrated circuit patterns.

[0096]FIG. 2 illustrates an example of the mask MK to transfer the holepattern of FIG. 1. FIG. 2(a) is a plan view of the essential portion ofthe mask MK and FIG. 2(b) illustrates the cross-sectional view along theline A1—A1 of FIG. 2(a). This mask MK is a reticle for transferring theoriginal image of an integrated circuit pattern in the size, forexample, of 1 to 10 times the actual size to the wafer through ademagnifying projection optical system or the like. A mask substrate 1of this mask MK is formed, for example, of a transparent syntheticquartz glass substrate or the like in the thickness of about 6 mm formedin the square plane. On the main surface of the mask substrate 1, ahalf-tone film (hatched area) 2 is deposited. The main aperture 3 and anauxiliary aperture 4 are formed by removing a part of the half-tone film2. These main aperture 3 and auxiliary aperture 4 are allocated at theintersecting points of the virtual lines (first and second virtuallines) Xm, Ym and these are regularly allocated in the condition to havethe periodicity in total. The virtual lines Xm, Ym are crossing inorthogonal with each other. The pitches Dmx, Dmy of the virtual linesXm, Ym are equal and are about 1 to 10 times the pitches Dwx, Dwy of thevirtual lines Xw, Yw on the wafer. The main aperture 3 is an aperturepattern to transfer the hole pattern H. The auxiliary aperture 4 is anaperture pattern not resolved on the wafer and its size on the plane isrelatively smaller than the size on the plane of the main aperture 3.The light beam having passed such main aperture 3 and auxiliary aperture4 and the light beam having the half-tone film 2 have a phase differenceof 180 degrees between them. At the time of aligning using such mask MK,a modified lighting is used as the light source of aligning. As thealigning method, any one of the scanning alignment, step and scanalignment and step and repeat alignment may be selected as desired.

[0097]FIG. 3 illustrates an example of the allocation on the plane ofcoarse and fine hole patterns in the wafer W. For example, in thesemiconductor IC device allowing coexistence of the memory circuit suchas DRAM (Dynamic Random Access Memory) or the like and the logic circuitand in the semiconductor IC device including CMIS (ComplementaryMIS)-logic, the coarse region and fine region co-exist in some cases onthe hole patterns of the same layer. FIG. 3 illustrates an example ofsuch condition. The left side of FIG. 3 is the fine region where thehole patterns H are allocated closely, while the right side of FIG. 3 isthe coarse region where the hole pattern H allocated coarsely. Theallocation condition of the hole patterns H is identical to thatexplained above. The size on the plane of the hole pattern H is, forexample, about 0.16×0.16 μm. The pitch of the hole patterns H (namely,the pitches Dwx, Dwy of the virtual lines Xw, Yw) is, for example, about0.32 μm.

[0098] FIGS. 4(a) and 4(b) illustrate an example of the mask MK totransfer the hole pattern H of FIG. 3. FIG. 4(a) is a plan view of theessential portion of the mask MK, while FIG. 4(b) is a cross-sectionalview along the line A2—A2 of FIG. 4(a). The light transmittingcoefficient of the half-tone film 2 is set, for example, to 3% to 20%,7% to 20% or 10 to 20%. In this embodiment, the light transmittingcoefficient is set, for example, to 7%. As explained above, the mainaperture 3 is an aperture pattern to transfer the hole patterns H. Theauxiliary apertures 4 are allocated in the manner that the centerthereof is overlapped at the intersecting points of the virtual linesXm, Ym in the circumference of the main apertures 3. In this embodiment,a positive bias is applied to the size of the main aperture 3 in bothfine and coarse regions to increase light beam intensity at the time ofalignment and thereby the size converted on the wafer of the mainaperture is set, for example, to about 200 nm×200 nm. Moreover, theauxiliary aperture 4 is set, for example, to about 140 nm×140 nm so thatit is not resolved at the time of alignment.

[0099] Next, an example of the method for manufacturing thesemiconductor IC device utilizing the mask MK of FIG. 4 will beexplained with reference to FIGS. 5 to 8. FIGS. 5(b), 6(b), 7(b) and8(b) are cross-sectional views along the line A3—A3 of FIGS. 5(a), 6(a),7(a) and 8(a), respectively. Here, an example of forming, for example, acontact hole as the hole pattern is explained.

[0100] First, as illustrated in FIGS. 5(a) and 5(b), the wafer W isformed, for example, of a silicon single crystal and an interlayerinsulation film 5 formed, for example, of a silicon oxide or the like isdeposited on the main plane (an element forming plane where elements areformed). On this interlayer insulation film 5, a photoresist film 6 isdeposited. The aligning process is executed to such wafer W using themask MK of FIG. 4. In this case, the modified lighting is used as thelight source of alignment. Thereby, a pattern of mask MK (pattern of themain aperture) is transferred to the photoresist film 6.

[0101] Subsequently, a photoresist pattern 6A is formed as illustratedin FIG. 6 by executing the developing process or the like to the waferW. The photoresist pattern 6A is formed in the manner that thephotoresist film 6 is removed to expose a part of the upper surface ofthe interlayer insulation film 5 in the contact hole forming region andthe other part is covered with the photoresist pattern 6A. The shape ofplane of the contract hole forming region where the interlayerinsulation film 5 is exposed in the photoresist pattern 6A is, forexample, almost circular.

[0102] Thereafter, the etching is conducted to the wafer W using thephotoresist pattern 6A as the etching mask. Thereby, as illustrated inFIG. 7, the interlayer insulation film 5 exposed from the photoresistpattern 6A is removed and contact holes CH are bored to the interlayerinsulation films 5 in both fine and coarse regions. Thereafter, thephotoresist pattern 6A is removed as illustrated in FIG. 8. The mainplane of wafer W or a part of the upper surface of gate electrode formedon the main plane of wafer W is exposed from the bottom part of thecontact hole CH. The shape of plane of the contact hole CH is, forexample, almost circular. The wafer W is finally divided, for example,into the semiconductor chips of the flat square shape.

[0103] FIGS. 9(a) and 9(b) illustrate the practical examples of the fineregion in the semiconductor IC device including the CMIS-logic circuit.FIG. 9(a) is a plan view of the essential portion of the semiconductorIC device, while FIG. 9(b) is a cross-sectional view along the lineA4—A4 of FIG. 9(a).

[0104] At the predetermined depth from the main plane of wafer W, thep-well PWL and n-well are formed. Moreover, at the main plane of waferW, a plurality of active regions L and an isolating region S surroundingthese active regions are formed. In the active regions L, nMISQn andpMISQn are formed. In addition, the isolating region S is formed, forexample, in the shape of groove (trench isolation). However, theisolating region S is not limited to the shape of groove and may beformed, for example, with a field insulation film using the LOCOS (LocalOxidation of Silicon) method.

[0105] On the main plane of the wafer W, a plurality of wirings 7extending in the upper and lower directions of FIG. 9 are allocated inparallel. The wirings 7 are formed, for example, of discrete film of lowresistance polysilicon, a polycide film where a silicide film such as acobalt silicide or the like is deposited on a low resistancepolysilicon, or of a polymetal film where a metal film such as tungstenor the like is deposited on a low resistance polysilicon via a barrierfilm such as tungsten nitride or the like. The pitch of the a adjacentwirings 7 is, for example, about 0.32 μm. In this wiring 7, the portionsoverlapping in the plane on the active region L are the gate electrodesG of nMISQn and pMISQp. The gate width is, for example, about 0.1 μm.Moreover, in the wiring 7, a region which is wider than the otherportion is formed to a portion overlapping in the plane on the isolatingregion S. Meanwhile, in the active region L, the portions overlapping inthe plane on the wiring 7 are channel regions of the nMISQn and pMISp.Moreover, in the active region L, both sides of gate electrode G are apair of semiconductor regions 8 for source and drain. In thesemiconductor region 8 of the nMISQn, phosphorus or arsenic, forexample, is doped and boron, for example, is doped to the semiconductorregion 8 of the pMISQp. Moreover, a gate insulation film 9 is providedbetween the lower surface of the gate electrode G and the main plane ofwafer W. The gate insulation film 9 is formed, for example, of a siliconoxide film, a laminated film of silicon nitride and silicon oxide or ofa high dielectric material film or the like.

[0106] On this main plane of the wafer W, an interlayer insulation film5 a formed, for example, of silicon oxide is deposited. On thisinterlayer insulation film 5 a, a plurality of contact holes CH (CH1,CH2) are allocated. The upper surface of the semiconductor region 8 isexposed from the bottom surface of the contact hole CH1. This controlhole CH1 is allocated in such a manner that the center thereof isoverlapped on the intersecting points of the virtual lines Xw, Yw. Onthe other hand, the upper surface of the wider region of wiring 7 isexposed from the bottom surface of the contact hole CH2. This controlhole CH2 is not allocated at the intersecting points of the virtuallines Xw and Yw but at the position deviated by a half-pitch in thelateral direction (extending direction of the virtual line Xw) of FIG. 9for such intersecting point, namely at the intermediate position betweenthe adjacent intersecting points in the lateral direction of FIG. 9. Abroken line in FIG. 9(b) indicates the first layer wiring 10A. The firstlayer wiring 10A is composed, for example, of aluminum, aluminum alloyor of metal film of tungsten or copper or the like and is electricallyconnected with the semiconductor region 8 or wiring 7 via the contactholes CH (CH1, CH2).

[0107] FIGS. 10(a) and 10(b) illustrate an example of the mask MK totransfer the contact hole CH of FIG. 9. FIG. 10(a) is a plan view of theessential portion of the mask MK, while FIG. 10(b) is a cross-sectionalview along the line A5—A5 of FIG. 10(a).

[0108] The main aperture (first main aperture) 3 a(3) is an aperturepattern to transfer the contact hole CH1 and is allocated on the mask MKin the manner that the center thereof overlaps on the intersecting pointof the virtual lines Xm, Ym. Moreover, the main aperture (second mainaperture) 3 b (3) is an aperture pattern to transfer the contact holeCH2. This main aperture 3 b is not allocated at the intersecting pointof the virtual lines Xm, Ym but at the position deviated by a half-pitchin the lateral direction (extending direction of the virtual line Xm) ofFIG. 10, namely at the intermediate position between the adjacentintersecting points in the lateral direction of FIG. 10. The sizes inthe planes of the main apertures 3 a, 3 b are equal with each other andis identical to the size in the plane of the main aperture 3.

[0109] On the other hand, the auxiliary aperture (first auxiliaryaperture) 4 a (4) is allocated on the mask MK in the manner that thecenter thereof overlaps on the intersecting point of the virtual linesXm, Ym. Moreover, the auxiliary aperture (second auxiliary aperture) 4 b(4) is not allocated at the intersecting point of the virtual lines Xm,Ym but at the position deviated by half-pitch in the lateral direction(extending direction of the virtual line Xm) of FIG. 10 for suchintersecting point, namely at the intermediate position between theadjacent intersecting points in the lateral direction of FIG. 10. Thesizes in the planes of auxiliary apertures 4 a, 4 b are equal with eachother and are identical to the size in the plane of the auxiliaryaperture 4.

[0110] As a modification example, the main aperture 3 b and auxiliaryaperture 4 b are allocated at the position deviated with the half-pitchin the extending direction of the virtual line Ym, namely at theintermediate position between the adjacent intersecting points in thevertical direction of FIG. 10.

[0111]FIG. 11 and FIG. 12 illustrate the practical examples of the fineregion of the semiconductor IC device including the DRAM-logic hybridcircuit. FIG. 11 is a plan view of the essential portion of the relevantsemiconductor IC device and FIG. 12 is a cross-sectional view along theline 6A—6A of FIG. 11.

[0112] The wafer W is formed, for example, of p-type silicon singlecrystal. A memory cell of DRAM is formed in the p-well PWL formed on thewafer W. The p-well PWL of the region (memory array) where a memory cellis formed is electrically isolated from the semiconductor substrate withan n-type semiconductor region 11 formed thereunder in order to prevententry of noise from an input/output circuit formed in the other regionof the semiconductor substrate forming the wafer W.

[0113] The memory cell is formed in the stacked structure in which aninformation accumulation capacitance element C is allocated at the upperpart of the MISFETQs for memory cell selection. The MISFETQs for memorycell selection is formed of nMIS and is formed within the active regionL of the p-well PWL. The active region L is formed of a pattern like anarrow island extending in straight along the X direction (correspondingto the extending direction of the virtual line Xw) of FIG. 11 and acouple of MISFETQs for memory cell selection are formed adjacently withany one of source and drain (semiconductor region 8) used in common inthe X direction of the respective active region L.

[0114] The isolating region S surrounding the active region L isstructured with a groove type element isolating portion (trenchisolation) that is formed by embedding the insulation film consisting ofsilicon oxide film in the shallow groove opened to the p-well PWL. Theinsulation film embedded in this groove type element isolating region Sis flattened at the surface. Since such groove type element isolatingregion S is does not form a bird's beak at the end portion of activeregion L, it is possible to obtain a larger effective area of the activeregion L in comparison with the isolating region (field oxide film) ofthe same size formed with the LOCOS (Local Oxidization of Silicon:selective oxidization).

[0115] The MISFETQs for memory cell section is mainly formed of a gateinsulation film 9, a gate electrode G and a pair of n-type semiconductorregions 8, 8 forming the source and drain. The gate electrode G isintegrally formed with the word line WL and is extended linearly alongthe Y direction (corresponding to the extending direction of the virtualline Yw) in the same width and the same space. The gate electrode G(word line WL) is formed, for example, in the polymetal structureexplained above. Since the gate electrode G (word line WL) of thepolymetal structure has an electric resistance that is lower than thatof the gate electrode structured with the polycrystalline silicon filmand polycide film, signal delay of the word line can be reduced.However, the gate electrode G may be structured with a discrete film ofthe polycrystalline silicon film or may be formed in the polycidestructure.

[0116] At the upper part of the gate electrode G (word line WL) of theMISFETQs for memory cell selection, a cap insulation film 14 consistingof the silicon nitride film or the like is formed and an insulation film15 consisting, for example, of the silicon nitride film is formed at theupper part and side wall of the cap insulation film 14 and the side wallof the gate electrode G (word line WL). The cap film 14 and insulationfilm 15 of the memory array are used as the etching stopper on theoccasion of forming the contact hole CH3 (CH) on the self-alignmentbasis for the gate electrode G at the upper part of the source and drain(n-type semiconductor regions 8, 8) of the MISFETQs for memory cellselection.

[0117] On the MISFETQs for memory cell selection, an interlayerinsulation film 5 b is formed. Moreover, on the interlayer insulationfilm 5 b, the interlayer insulation films 5 c, 5 d consisting of thedouble-layer silicon oxide or the like are formed and the surface of theupper insulation film 5 d is flattened. At the upper part of a pair ofn-type semiconductor regions 8, 9 forming the source and drain of theMISFETQs for memory cell selection, a contact hole CH3 (CH) is formedthrough the interlayer insulation films 5 d, 5 c, 5 b. The plainallocation of the contact hole CH3 conforms to the allocation conditionsexplained above. Moreover, structure of the mask used to form thecontact hole CH3 is also identical to that explained above. In addition,a method to form the contact hole CH3 is also identical to that for thecontact hole CH and therefore same explanation is omitted here. At theinside of such contact hole CH3, for example, a plug 16 a that is formedof the phosphorus(P)-doped polycrystalline silicon film of lowresistance is embedded. The size in the X direction of the bottomportion of the contact hole CH3 is specified with the space of theinsulation film 15 at one side wall and the insulation film 15 of theother side wall of the two gate electrodes G (word line WL) providedopposed with each other. Namely, the contact hole CH3 is formed on theself-alignment basis for the gate electrode G (word line WL).

[0118] The size of one contact hole CH3 in the Y direction (verticaldirection in FIG. 11) among the contact holes CH3, CH3 is almostidentical to the size in the Y direction of the active region L. On theother hand, a diameter in the Y direction of the other contact hole CH3(contact hole on the n-type semiconductor region 8 used in common withthe two MISFETQs for memory cell selection) is larger than the size ofthe active region L in the Y direction. Namely, the contact hole CH3 isstructured with an almost rectangular plane pattern in which thediameter in the Y direction is larger than the diameter in the Xdirection (lateral direction in FIG. 11) and a part of this contact holeCH3 is deviated from the active region L and is extending in the plainon the groove type isolating region S. Since the contact hole CH3 isformed in such a pattern, it is no longer required to extending the bitline BL up to the upper part of the active region L by partly makingthick the width of this bit line and to extend a part of the activeregion L in the direction of the bit line BL. Thereby, a memory size canbe reduced.

[0119] An insulation film 5 e is deposited on the insulation film 5 d.On the insulation film 5 e on the contact hole CH3, a through-hole TH1is formed and a plug that is formed of a conductive film sequentiallylaminating Ti (titanium) film, TiN (titanium nitride) film and W(tungsten) film from the lower side is embedded in this through-holeTH1. The through-hole TH1 is allocated at the upper part of the groovetype isolating region S deviated from the active region L. The plainallocation of this through-hole TH1 conforms to the allocation conditionof the contact hole CH. Moreover, the structure of mask used to form thethrough-hole TH1 is also identical to that of mask used to form thecontact hole CH. Moreover, a method of forming the through-hole TH1 isalso identical to that of the contact hole CH and the same explanationis omitted here.

[0120] On the interlayer insulation film 5 e, a bit line BL is formed.The bit line BL is allocated at the upper part of the groove typeelement isolating region S and is linearly extending along the Xdirection in the same width and same space. The bit line BL is formed,for example, of the tungsten film and is electrically connected with one(n-type semiconductor region 8 used in common with the two MISFETQs formemory cell selection) of the source and drain of the MISFETQs formemory cell selection through the contact hole CH3 formed at thethrough-hole TH1, interlayer insulation films 5 e, 5 d, 5 c, 5 b at thelower part of the through-hole and the gate insulation film 9.

[0121] On the bit line BL, the interlayer insulation films 5 f, 5 gconsisting, for example, of silicon oxide are formed. The surface of theupper interlayer insulation film 5 g is flattened. On the interlayerinsulation film 5 g of the memory cell array, an interlayer insulationfilm 5 h consisting of the silicon nitride or the like is formed andmoreover a capacitance element C for information accumulation is formedthereon. The capacitance element C for information accumulation isstructured with a lower electrode (accumulation electrode) 17 a, anupper electrode (plate electrode) 17 b and a capacitance insulation film(dielectric material film) 17 c consisting of Ta₂O₅ (tantalum oxide)provided between such upper and lower electrodes. The lower electrode 17a is formed, for example, of the phosphorus(P)-doped low resistancepolycrystalline silicon film and the upper electrode 17 b is formed, forexample, of the TiN film . The lower electrode 17 a of the elementcapacitance C for information accumulation is electrically connectedwith a plug 16 a in the contact hole CH3 via the plug 16 b embedded inthe through-hole TH2 provided through the insulation film 5 h and theinsulation films 5 g, 5 f, 5 e at the lower layer of this insulationfilm and moreover is also connected electrically to the other of thesource and drain (semiconductor region 8) of the MISFETQs for memorycell selection via the plug 16 a.

[0122] At the upper part of the capacitance element for informationaccumulation, an interlayer insulation film 5 i consisting ofdouble-layer silicon oxide or the like and moreover the second layerwiring 10B is formed thereon. On this second layer wiring 10B, theinterlayer insulation films 5 j, 5 k consisting of the double-layersilicon oxide or the like are also formed. On the interlayer insulationfilm 5 k, the third layer wiring 10C is formed. The second and the thirdlayer wirings 10B, 10C are structured, for example, of a conductive filmmainly composed, for example, of aluminum (Al) alloy.

[0123] Next, an example of aligner used in this embodiment will beexplained with reference to FIG. 13 and FIG. 14.

[0124] For example, the aligning conditions of the aligner 20 are asfollows. Namely, as the light beam for alignment of the aligner 20 a,for example, KrF excimer laser beam (alignment wavelength λ=248 nm) isused. However, the aligning laser beam is not limited to that explainedabove and various laser beams can be used. For example, it is alsopossible to use the ArF excimer laser in the wavelength of 193 nm and F₂laser in the wavelength of 157 nm. The numerical aperture NA of anoptical lens is set, for example, to 0.6. As the aligning method, forexample, the scanning alignment, step and scan alignment or step andrepeat alignment may be used.

[0125] The laser beam emitted from the aligning source 20 a radiates amask MK via a fly-eye lens 20 b, an aperture 30 c, condenser lenses 20 d1, 20 d 2 and a mirror 20 e. Among the optical conditions, shape of theopening of aperture 20 c is adjusted depending on the shape of themodified lighting of FIG. 14. Since depth of focus and alignmentallowance can be improved both in the coarse region and fine region byutilizing the mask of the structure explained above, resolution can alsobe improved. Moreover, pattern size difference resulting from sizevariation for deviation of focus and coarse or fine condition ofpatterns can also be reduced. Moreover, it is also possible that theauxiliary aperture on the mask is not resolved on the wafer for thepredetermined exposure. FIG. 14(a) illustrates the 4-aperture lighting,while FIG. 14(b) illustrates the ring-belt lighting. In the 4-aperturelighting and ring-belt lighting, the distance LD of the center ofaperture from the optical axis is set, for example, to about 0.65. Theradius of aperture in the 4-aperture lighting is set, for example, toabout 0.2. The optimum value of the distance LD is LD=(1/(2D)) λ/NA. Dis the pitch Dwx, Dwy of the virtual line Xw, Yw. For example, abovevalues are substituted for the above formula,LD=(½×0.32)0.248/0.6=0.645. Therefore, it is approximated to about 0.65.Here, Dwx Dwy. In the case of the 4-aperture lighting, since theaperture is optimized to the period pattern pitch in the vertical andlateral directions required, good aligning condition may be attained.Moreover, in the case of ring-belt lighting, the aperture is optimizedto the period pattern pitch in the vertical and lateral directionsrequired and moreover the aperture corresponds to the pattern pitch inthe other oblique direction, resulting in flexibility from the practicalviewpoint.

[0126] On the mask MK of FIG. 13, a pellicle PE is provided to preventgeneration of pattern transfer fault or the like due to adhesion offoreign material. A mask pattern depicted on the mask 26 is projected onthe wafer W as the sample substrate via a projection lens 20 f. Here,the mask MK is placed on a mask stage 20 h controlled with a maskposition control means 20 g and the thereof and the optical axis of theprojection lens 20 f are in the accurate positioning condition. Thewafer W is vacuum-attracted on the wafer stage 20 i. The wafer stage 20i is placed on a Z stage 20 j which may be movable in the optical axisdirection of the projection lens 20 f, namely in the Z direction andmoreover placed on the XY stage 20 k. Since the Z stage 20 j and XYstage 20 k are driven with respective drive means 20 n 1, 20 n 2depending on the control instruction from a main control system 20 m,these can be moved to the desired aligning position. Such aligningposition is accurately monitored with a laser measuring device 20 q asthe position of a mirror 20 p fixed to the Z stage 20 j. Moreover, thesurface position of the wafer W (substrate 1) is measured with a focalposition detecting means provided in an ordinary aligner. The surface ofwafer W can always be matched with the focusing plane of the projectionlens 20 f by driving the Z stage 20 j depending on the result ofmeasurement.

[0127] On the occasion of overlay alignment of the circuit pattern onthe mask MK for the circuit pattern formed on the wafer W, position ofthe mark pattern formed on the wafer W is detected with an alignmentdetection optical system 20 r and the overlay transfer is performedafter the positioning of the wafer W based on the result of detection.The main control system 20 m is electrically connected with a networkapparatus 20 s to enable remote monitoring of the conditions of thealigner 20.

[0128]FIG. 15 illustrates a result of comparison of the focus depthcharacteristic (dependence on deviation of focus of the hole diameter)based on the simulation in such cases that the mask of the presentinvention (half-tone mask) is used and that the mask discussed with theinventors of the present invention (for example, the techniquerepresented by Japanese Unexamined Patent Publication No. 135402/1999:binary mask) is used. The optical proximity effect (OPC) will beexplained in regard to the other embodiments explained later.

[0129] Aligning intensity of simulation has been determined to provide adiameter of the transfer pattern (hole pattern) of the fine pattern ofabout 0.16 μm when the focus deviation is zero (0). In regard to thefine pattern, it is overlapped when the mask of the present invention isused (black triangle) and when the mask discussed by the inventors ofthe present invention is used (black square) and there is no preferencebetween such masks. On the other hand, in regard to the coarse pattern,when the mask of the present invention is used (white triangle) is used,the pattern size difference is more improved by about 7 nm than thatwhen the mask discussed by the inventors of the present invention (whitesquare) is used.

[0130]FIG. 16 illustrates a result of simulation of hole patterndiameter in the coarse region for the exposure. The white triangle andsquare plots indicate that the auxiliary aperture on the mask isresolved. Determination for resolution or not of auxiliary aperture ismade considering the margin to provide a result that aligning intensityat the auxiliary aperture becomes 80% or less of the resolved alignmentintensity for the non-resolution purpose. In the technique discussed bythe inventors of the present invention, application is impossiblebecause the auxiliary aperture of mask is resolved on the wafer with theexposure in which hole pattern diameter is about 160 nm that has beendesired. On the other hand, in the mask of the present invention, it canbe understood that application is possible because the auxiliaryaperture of mask is not resolved.

[0131] As explained above, according to the embodiment 1 of the presentinvention, following effects can be attained.

[0132] (1) Resolution of pattern can be improved by using the mask ofthe structure explained above and the modified lighting for thealignment process.

[0133] (2) Size difference of pattern in the coarse and fine regions canbe reduced by using the mask of the structure explained above and themodified lighting for the alignment process.

[0134] (3) Size accuracy of pattern can be improved by using the mask ofthe structure explained above and modified lighting for the alignmentprocess.

[0135] (4) Performance and reliability of semiconductor IC device can beimproved based on the above items (1) to (3).

[0136] (Embodiment 2)

[0137] In the case of the mask of the present invention in the structureexplained above, a size difference between the coarse and fine patternsis as large as about 20 nm and the hole pattern H of FIG. 3 cannot beformed in some cases with the size accuracy of ±10%.

[0138] Therefore, in this embodiment, the proximity correction isadapted. Here, it is preferable that this proximity correction isconducted to the main aperture to which the main aperture to transferthe other hole pattern is not allocated in the periphery among the mainaperture on the mask to transfer the hole pattern in the coarse regionand the main aperture on the mask to transfer the hole pattern in thefine region or to both main apertures explained above. The otherstructure is same as that in the embodiment 1.

[0139]FIG. 17 illustrates an example of the plan view of the essentialportion of the wafer having the hole pattern H formed by using the maskof this embodiment.

[0140] FIGS. 18(a) and 18(b) illustrate an example of the mask used toform the hole pattern H of this embodiment. FIG. 18(a) is a plan view ofthe essential portion of mask and FIG. 18(b) is a cross-sectional viewalong the line A7—A7 of FIG. 18(a).

[0141] An OPC value Δdopc (Left) of the main aperture 3 at the mask MKto form the hole pattern H allocated at the intersecting point P1 of thevirtual lines Xw, Yw on the wafer W can be obtained by accumulating thecorrection value determined with the relative positions of therespective intersecting points P1, P2, P3, P4 depending on existence orno-existence of the hole pattern at the intersecting points P2, P3, P4of the virtual lines Xw, Yw on the wafer. In this example, the holepattern is not allocated at the intersecting points P2, P3 and thecorrection values are accumulated respectively. The main aperture 3 a 1of the mask MK of FIG. 18 indicates the aperture pattern before theproximity correction, while the main aperture 3 a 2 indicates theaperture pattern after the proximity correction. The size of the mainaperture 3 a 2 after the proximity correction is larger than that of theother main aperture 3.

[0142] The effect of adaptation of the proximity correction to the mainaperture 3 of the mask MK of FIG. 4 to form the hole pattern H of thecoarse region of FIG. 3 has been obtained with the simulation. The planesize converted on the wafer of the auxiliary aperture 4 is, for example,to about 140 nm×150 nm as explained above and the proximity correctionΔdopc in each direction is set, for example, to about 10 nm, while theplane size converted on the wafer of the main aperture 3 is set, forexample, to about 220 nm×220 nm. As a result, as indicated in the focusdepth characteristic of FIG. 15, the depth of focus becomes ±0.3 m whenthe size accuracy of pattern is ±10% and thereby the hole pattern H ofthe coarse region of FIG. 3 can be transferred. Namely, according tothis embodiment, the effect that the hole pattern H located at theboundary of the coarse and fine regions can be formed with the sizeaccuracy of ±10% can be obtained in addition to the effects attained inthe embodiment explained above.

[0143] As a modification example, there is provided a structure wherethe half-tone film 2 of mask MK is replaced with a light shielding filmconsisting, for example, of a discrete film of chromium or a laminatedlayer film of chromium and chromium oxide. In this case, the effectexplained above can also be attained.

[0144] (Embodiment 3)

[0145] In the embodiment 2 explained above, the proximity correction isadapted to the main aperture of mask. In this embodiment, the proximitycorrection is conducted to the auxiliary aperture of mask with the samereason as the embodiment 2.

[0146]FIG. 19 is a plan view of the essential portion of the wafer Wincluding the hole pattern H formed by using the mask of thisembodiment. FIGS. 20(a) and 20(b) illustrate an example of the mask MKused to form the hole pattern H of this embodiment. FIG. 20(a) is a planview of the essential portion of the mask MK, while FIG. 20(b) is across-sectional view along the line A8—A8 of FIG. 20(a).

[0147] In this example, the hole pattern H is not allocated at theintersecting point P5 of the virtual lines Xw, Yw on the wafer W. In themask MK of FIG. 20, the auxiliary aperture 4 (4 a 1, 4 a 2) is allocatedat the position corresponding to the intersecting point P5 on the waferW of FIG. 19. This auxiliary aperture 4 a 1 indicates the aperturepattern before the proximity correction, while the auxiliary aperture 4a 2, the aperture pattern after the proximity correction. An OPC valueΔdopc (Left) for the auxiliary aperture 4 a 1 can be obtained byaccumulating the correction values determined with the relativepositions of the respective intersecting points P5, P6, P7, P8 dependingon existence and no-existence of the hole pattern at the intersectingpoints P6, P7, P8 of the virtual lines Xw, Yw on the wafer W of FIG. 19.In this example, the hole pattern is not allocated at the intersectingpoints P6, P7 and the respective correction values are accumulated. Sizeof the auxiliary aperture 4 a 2 after the proximity correction is alittle larger than that before the correction. With this correction, theauxiliary aperture 4 in the periphery of the main aperture 3 to form thehole pattern becomes larger in the coarse region, difference between thecoarse and fine regions may be reduced. Moreover, a margin for thenon-resolution of the auxiliary aperture 4 in the fine region can alsobe improved because the auxiliary aperture 4 in the fine region becomessmall relatively.

[0148] As a modification example in this embodiment 3, the half-tonefilm 2 of the mask MK may be replaced with a light shielding film, forexample, of discrete film of chromium or a laminated film of chromiumand chromium oxide. Moreover, it is also possible to combine thismodification example with the modification example explained in theembodiment 2. In this case, the effect as explained above can also beobtained.

[0149] (Embodiment 4)

[0150] In this embodiment, an example of the method to allocate theauxiliary apertures on the mask will be explained.

[0151]FIG. 21 schematically illustrates the design data of the holepattern H. Here, an example of allocation of the hole pattern H in thecoarse region (right side of FIG. 21) and the fine region (left side ofFIG. 21). The hole pattern H is allocated at the intersecting points ofthe virtual lines Xw, Yw.

[0152] In this embodiment, the intersecting points surrounding aboveintersecting points where the hole pattern H is allocated are defined asthe allocation region B (hatched region) of the auxiliary aperture onthe mask and the auxiliary apertures are allocated at the intersectingpoints where the hole pattern H is not allocated in this allocationregion B. This allocation region B is automatically formed by broadeningthe hole pattern H up to two times the pattern pitch.

[0153] FIGS. 22(a)and 22(b) illustrate the mask MK generated with theallocation method explained above. FIG. 22(a) is a plan view of theessential portion of the mask MK and FIG. 22(b) is a cross-sectionalview along the line A9—A9 of FIG. 22(a). The auxiliary apertures 4 areallocated to surround the main apertures 3 at the intersecting points ofthe virtual lines Xm, Ym around the main apertures 3 to transfer thehole pattern H.

[0154] As explained above, the effective region of the auxiliaryapertures 4 is determined and the auxiliary apertures 4 are allocatedtherein. Thereby, it can be prevented that useless auxiliary apertures 4are formed. Therefore, it can also be prevented to depict uselesspattern at the time of fabricating the mask. Accordingly, the patterndepicting time of the mask MK can be shortened and thereby the mask MKmanufacturing time can also be shortened. As a result, the developmentperiod and manufacturing period of a semiconductor IC device can beshortened.

[0155] Such method to allocate the auxiliary apertures on the mask canalso be adapted to the mask utilizing a discrete film of chromium or alaminated layer film of chromium and chromium oxide or the like as thelight shielding film. Moreover, it is also possible to combine thismethod with the modification examples explained in the embodiments 2 and3. When these are combined, the similar effect can also be attained.

[0156] (Embodiment 5)

[0157] In this embodiment, a part of the allocation of the virtual linesis deviated.

[0158]FIG. 23 is a plan view of the essential portion of the wafer Wwhere a plurality of hole patterns H are allocated. In the regions C, Dof wafer W, the virtual line Xw is allocated in the same pitch withoutany deviation. However, the virtual line Yw1 in the region C is providedin the same interval as the virtual line Yw2 in the region D but thepitch thereof is deviated by a half-pitch from that of the virtual lineYw2.

[0159]FIG. 24(a) is a plan view of the essential portion of mask MK inthe case of transferring the hole pattern of FIG. 23. FIGS. 24(b) and24(c) are explanatory diagrams for correction of the main aperture 3 inthe cases where the pattern allocation is fine and coarse. Thecross-section of the mask MK is identical to that explained above. Thevirtual lines Ym1, Ym2 are also deviated by a half-pitch.

[0160] In this case, it is also preferable to conduct proximitycorrection explained in the embodiments 2, 3 for the apertures (mainaperture 3 and auxiliary aperture 4) allocated in the regioncorresponding to the boundary region of the regions C and D of FIG. 23.Correction for the apertures at the boundary region is different fromthat for the apertures (main aperture 3 and auxiliary aperture 4)allocated in the region other than the boundary region explained above.For example, the OPC value ΔDopc (edge) of the main aperture 3 in themask MK to form the hole pattern H allocated at the intersecting pointP9 of the virtual lines Xw and Yw2 on the wafer, for example, at theboundary region can be obtained by accumulating the correctiondetermined from the relative positions of the intersecting points P9,P10, P11 depending on existence or non-existence of the hole patterns atthe intersecting points P10, P11 of the virtual lines Xw, Yw1 on thewafer. In the case where the hole pattern H is about a half of thepattern pitch (in the case of fine allocation), the value of ΔDopc(edge) is preferably smaller than the OPC value in the region other thanthe boundary region explained above (FIG. 24(b)). Moreover, when thepitch in the X direction of the hole pattern H is large (coarseallocation), it is preferable that the value of ΔDopc (edge) isidentical to or larger than the OPC value of the region other than theboundary region (FIG. 24(c)). The OPC value is also determined in thesame manner for the auxiliary apertures 4. In FIG. 24(a), an examplewhere correction is executed only to one main aperture 3 is illustratedbut in actual the correction is also executed to the main apertures 3and auxiliary apertures 4 in the boundary region (region surrounded witha broken line).

[0161] Thereby, even if there is deviation in the pattern allocation,the pattern transfer may be performed accurately. Therefore, thisembodiment can be adapted to the actual pattern transfer of thesemiconductor IC device. Moreover, this embodiment assures improvementin reliability and manufacturing yield of the semiconductor IC device.

[0162] A method for covering such pattern deviation can also be adaptedto the mask using, as the light shielding film, a discrete film ofchromium or a laminated film of chromium and chromium oxide or the like.Moreover, it is also possible to combine this embodiment with themodification examples of the embodiments 2 to 4. In this case, thesimilar effect can also be attained.

[0163] (Embodiment 6)

[0164] In this embodiment, an example where the vertical and lateralpitches of the virtual lines are different will be explained.

[0165]FIG. 25 is a plan view of the essential portion of the wafer W.Here, the pitches Dwy, Dwx of the virtual lines Xw, Yw are different andthe pitch Dwx is longer than the pitch Dwy. Moreover, FIG. 26 is a planview of the essential portion of the mask MK in the case of FIG. 25. Thepitches Dmy, Dmx of the virtual lines Xm, Ym are different and the pitchDmx is longer than the pitch Dmy. Moreover, FIG. 27 illustrates the4-aperture lighting as an example of the lighting system of the alignerused in this case. The distance LD from the optical axis of the centerof the aperture in the 4-aperture lighting is as explained above. Here,the vertical and lateral pitches Dwx, Dwy of the virtual lines can bedetermined independently and the optimum values of the distances LDx,Ldy from the optical axis of the center of aperture in the 4-aperturelighting can also be determined depending on the respective pitches. InFIG. 27, the distances LDx, Ldy are different and the distance LDy islonger than the distance LDx.

[0166] Moreover, in this case, the proximity correction is alsoconducted independently in the vertical and lateral directions of thevirtual lines Xm, Ym. As illustrated in FIG. 25, when the lateral pitchDxw is larger and the desired hole pattern H is in the same size in thevertical and lateral directions, it is preferable that the proximitycorrection value in the vertical direction is set larger than that inthe lateral direction.

[0167] Thereby, accurate pattern transfer can be realized even when thevertical and lateral pitches of the virtual lines are different.Therefore, the method of this embodiment can also be adapted to theactual pattern transfer of a semiconductor IC device. In addition,reliability and manufacturing yield of the semiconductor IC device canbe improved.

[0168] The method for covering such difference of the vertical andlateral pitches of the virtual lines can also be adapted the mask using,as the light shielding film, of a discrete film of chromium or alaminated layer film of chromium and chromium oxide or the like. Inaddition, it is also possible to combine this method with themodification examples of embodiments 2 to 5. In such a case, the similareffect can also be attained.

[0169] The present invention has been explained practically based on thepreferred embodiments thereof, but the present invention is not limitedonly to the embodiments explained above and allows various changes ormodifications without departing from the scope of the claims thereof.

[0170] For example, in above embodiments, a crown type capacitor is usedfor the memory cell of DRAM, but the present invention is not limitedthereto and allows various changes. For example, it is also possible usea fin type capacitor.

[0171] Moreover, in above embodiments, an ordinary wiring structure isused but the present invention is not limited thereto. For example, thepresent invention can also be adapted to the so-called the Damascenewiring structure to for the wiring and plug, for example, by embeddingthe conductor film into the groove or hole bored in the insulation film.

[0172] In above explanation, the present invention has been adapted tothe manufacturing of a semiconductor IC device including the CMIS-logicor a semiconductor IC device including the DRM-logic hybrid circuit asthe typical application field thereof, but the present invention is notlimited thereto and can also be adapted to manufacturing of asemiconductor IC device including a memory circuit such as SRAM (StaticRandom Access Memory) or flash memory (EEPROM: Electric ErasableProgrammable Read Only Memory) or the like, a semiconductor IC deviceincluding a logic circuit such as a microprocessor or the like and ahybrid type semiconductor IC device providing the memory circuit andlogic circuit on the same semiconductor substrate.

[0173] The representative effects of the present invention will besummarized as follows.

[0174] (1) According to the present invention, the resolution of thepredetermined pattern can be improved by, on the occasion of thealigning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating the photoresist film on thesemiconductor wafer with an aligning laser beam of the modified lightingvia the photomask, utilizing the photomask thereof allocating, toprovide the periodicity, the main apertures to transfer thepredetermined pattern as the apertures formed by removing a part of thehalf-tone film on the mask substrate and the auxiliary apertures notresolved on the semiconductor wafer as the apertures formed by removinga part of the half-tone film.

[0175] (2) According to the present invention, on the occasion of thealigning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating the photoresist film on thesemiconductor wafer with the aligning laser beam of the modifiedlighting via the photomask, the pattern size difference in the coarseregion where the predetermined patterns are allocated in the relativelycoarse condition and the fine region where the predetermined patternsare allocated in the relatively fine condition can be reduced byutilizing the photomask thereof allocating, to provide the periodicity,the main apertures to transfer the predetermined pattern as theapertures formed by removing a part of the half-tone film on the masksubstrate and the auxiliary apertures not resolved on the semiconductorwafer as the apertures formed by removing a part of the half-tone film.

[0176] (3) According to the present invention, on the occasion of thealigning process to transfer the predetermined pattern to thesemiconductor wafer by irradiating the photoresist film on thesemiconductor wafer with the aligning laser beam of the modifiedlighting via the photomask, the size accuracy of pattern existing at theboundary of the coarse region where the predetermined patterns areallocated in the relatively coarse condition and the fine region wherethe predetermined patterns are allocated in the relatively finecondition can be improved by utilizing the photomask thereof allocatingto provide periodicity, the main apertures to transfer the predeterminedpattern as the apertures formed by removing a part of the half-tone filmon the mask substrate and the auxiliary apertures not resolved on thesemiconductor wafer as the apertures formed by removing a part of thehalf-tone film.

What is claimed is:
 1. Method for manufacturing a semiconductor ICdevice, comprising the steps of: (a) depositing a photoresist on asemiconductor wafer and (b) transferring the predetermined pattern tothe semiconductor wafer by irradiating the photoresist film on saidsemiconductor wafer with an aligning laser beam of the modified lightingvia the photomask; wherein said photomask comprises a mask substrate, ahalf-tone film formed on the main surface thereof, main apertures totransfer the predetermined pattern as the apertures formed by removing apart of said half-tone film and auxiliary apertures not resolved on saidsemiconductor wafer as the apertures formed by removing a part of saidhalf-tone film and said main apertures and auxiliary apertures areallocated to provide periodicity.
 2. Method for manufacturing asemiconductor IC device according to claim 1, wherein said mainapertures and auxiliary apertures are allocated at the intersectingpoints of the first and second virtual lines crossing with each other.3. Method for manufacturing a semiconductor IC device according to claim2, wherein the pitch structures of said first and second virtual linesare identical in different regions on the main surface of said photomaskand the positions of said different regions are deviated.
 4. Method formanufacturing a semiconductor IC device according to claim 2, whereinthe pitch of said first virtual line is different from the pitch of saidsecond virtual line.
 5. Method for manufacturing a semiconductor ICdevice according to claim 4, wherein a modified lighting is useddepending on the pitch structures of said first and second virtual linesfor the aligning process to transfer said predetermined pattern. 6.Method for manufacturing a semiconductor IC device according to claim 2,wherein the first main aperture and the first auxiliary aperture amongsaid main apertures and auxiliary apertures are allocated at theintersecting points of said first and second virtual lines, while thesecond main aperture and auxiliary aperture among said main aperturesand auxiliary apertures are allocated between adjacent lines of saidfirst virtual lines, or between the adjacent lines of said secondvirtual lines or to both adjacent lines of said first and second virtuallines.
 7. Method for manufacturing a semiconductor IC device accordingto claim 1, wherein the proximity correction is applied to thepredetermined main apertures among said main apertures or to thepredetermined auxiliary apertures among said auxiliary apertures or toboth predetermined main and auxiliary apertures.
 8. Method formanufacturing a semiconductor IC device according to claim 1, whereinsaid auxiliary aperture allocating region is broadened for the length ofinteger times the pitch of said predetermined pattern with reference tosaid main apertures.
 9. Method for manufacturing a semiconductor ICdevice according to claim 1, wherein said modified lighting is the4-aperture lighting or the ring-belt lighting.
 10. Method formanufacturing a semiconductor IC device according to claim 1, whereinthe coarse region where said predetermined pattern is allocated in therelatively coarse condition and the fine region where said predeterminedpattern is allocated in the relatively fine condition co-exist on thesame layer in the predetermined region of said semiconductor wafer. 11.Method for manufacturing a semiconductor IC device according to claim 1,wherein said predetermined pattern is a hole pattern.
 12. Method formanufacturing a semiconductor IC device, comprising the steps of: (a)depositing a photoresist on a semiconductor wafer and (b) transferringthe predetermined pattern to the semiconductor wafer by irradiating thephotoresist film on said semiconductor wafer with an aligning laser beamof the modified lighting via the photomask; wherein said photomaskcomprises a mask substrate, a light shielding film formed on the mainsurface thereof, main apertures to transfer the predetermined pattern asthe apertures formed by removing a part of said light shielding film andauxiliary apertures not resolved on said semiconductor wafer as theapertures formed by removing a part of said light shielding film andsaid main apertures and auxiliary apertures are allocated to provideperiodicity; and the proximity correction is applied to saidpredetermined main apertures among said main apertures, saidpredetermined auxiliary apertures among said auxiliary aperture or toboth said predetermined main and auxiliary apertures.
 13. Method formanufacturing a semiconductor IC device according to claim 12, whereinsaid main apertures and auxiliary apertures are allocated at theintersecting points of the first and second virtual lines which arecrossing with each other.
 14. Method for manufacturing a semiconductorIC device according to claim 13, wherein the pitch structures of saidfirst and second virtual lines in different regions on the main surfaceof said photomask are identical and positions of said different regionsare deviated.
 15. Method for manufacturing a semiconductor IC deviceaccording to claim 13, wherein the pitch of said first virtual line isdifferent from the pitch of said second virtual line.
 16. Method formanufacturing a semiconductor IC device according to claim 15, whereinthe modified lighting is used depending on the pitch structures of saidfirst and second virtual lines for the aligning process to transfer saidpredetermined pattern.
 17. Method for manufacturing a semiconductor ICdevice according to claim 13, wherein the first main aperture and thefirst auxiliary aperture among said main apertures and auxiliaryapertures are allocated at the intersecting points of said first andsecond virtual lines, while the second main aperture and auxiliaryaperture among said main apertures and auxiliary apertures are allocatedbetween adjacent lines of said first virtual lines, or between theadjacent lines of said second virtual lines or to both adjacent lines ofsaid first and second virtual lines.
 18. Method for manufacturing asemiconductor IC device according to claim 12, wherein said auxiliaryaperture allocating region is broadened for the length of integer timesthe pitch of said predetermined pattern with reference to said mainapertures.
 19. Method for manufacturing a semiconductor IC deviceaccording to claim 12, wherein said modified lighting is the 4-aperturelighting or ring-belt lighting.
 20. Method for manufacturing asemiconductor IC device according to claim 12, wherein the coarse regionwhere said predetermined pattern is allocated in the relatively coarsecondition and the fine region where said predetermined pattern isallocated in the relatively fine condition co-exist on the same layer inthe predetermined region of said semiconductor wafer.
 21. Method formanufacturing a semiconductor IC device according to claim 12, whereinsaid predetermined pattern is a hole pattern.
 22. Method formanufacturing a semiconductor IC device, comprising the steps of: (a)depositing a photoresist on a semiconductor wafer and (b) transferringthe predetermined pattern to the semiconductor wafer by irradiating thephotoresist film on said semiconductor wafer with an aligning laser beamof the modified lighting via the photomask; wherein said photomaskcomprises a mask substrate, a light shielding film formed on the mainsurface thereof, main apertures to transfer the predetermined pattern asthe apertures formed by removing a part of said light shielding film andauxiliary apertures not resolved on said semiconductor wafer as theapertures formed by removing a part of said light shielding film andsaid main apertures and auxiliary apertures are allocated to provideperiodicity; and said auxiliary aperture allocating region is broadenedfor the length of integer times the pitch of said predetermined patternwith reference to said main apertures.
 23. Method for manufacturing asemiconductor IC device according to claim 22, wherein said mainapertures and auxiliary apertures are allocated at the intersectingpoints of the first and second virtual lines which are crossing witheach other.
 24. Method for manufacturing a semiconductor IC deviceaccording to claim 23, the pitch structures of said first and secondvirtual lines are different for every regions on the main surface ofsaid photomask.
 25. Method for manufacturing a semiconductor IC deviceaccording to claim 23, wherein the pitch of said first virtual line isdifferent from the pitch of said second virtual line.
 26. Method formanufacturing a semiconductor IC device according to claim 25, whereinthe modified lighting is used depending on the pitch structures of saidfirst and second virtual lines for the aligning process to transfer saidpredetermined pattern.
 27. Method for manufacturing a semiconductor ICdevice according to claim 23, wherein the first main aperture and thefirst auxiliary aperture among said main apertures and auxiliaryapertures are allocated at the intersecting points of said first andsecond virtual lines, while the second main aperture and auxiliaryaperture among said main apertures and auxiliary apertures are allocatedbetween adjacent lines of said first virtual lines, or between theadjacent lines of said second virtual lines or to both adjacent lines ofsaid first and second virtual lines.
 28. Method for manufacturing asemiconductor IC device according to claim 22, wherein said modifiedlighting is the 4-aperture lighting or ring-belt lighting.
 29. Methodfor manufacturing a semiconductor IC device according to claim 22,wherein the coarse region where said predetermined pattern is allocatedin the relatively coarse condition and the fine region where saidpredetermined pattern is allocated in the relatively fine conditionco-exist on the same layer in the predetermined region of saidsemiconductor wafer.
 30. Method for manufacturing a semiconductor ICdevice according to claim 22, wherein said predetermined pattern is ahole pattern.